1. Field of Invention
The present invention relates to a field of a sampling circuit, and more particularly to a sample-and-hold circuit for ADC (Analog-to-Digital Converter).
2. Description of Related Arts
In the circuit for ADC (Analog-to-Digital Converter), in order to ensure the accuracy and speed of the ADC, the input sampling terminal have to employ a bootstrap structure to ensure the linearity of the input sampling switch and to expand the range of the input signal as well. However, while adopting the sampling circuit having the bootstrap structure, error introduced by the clock feedthrough is related to the signals inputted, and thus non-linear error is introduced, and the impact of the clock feedthrough is not capable of being eliminated by adopting a fully-differential structure amplifier.
Referring to FIG. 1 of the drawings, the conventional sampling circuit for ADC comprises a clock circuit, a sampling circuit and a capacitor C0, wherein the clock circuit generates clock pulses and outputs the clock pulses generated thereby to the sampling circuit via an output terminal K0 thereof, so as to control sampling operation of the sampling circuit by the clock pulses. The sampling circuit comprises a bootstrap unit and a field effect transistor (FET) M1, wherein two input terminals of the bootstrap unit are respectively connected with an output terminal K0 of the clock circuit and an external input terminal, the external input terminal inputs a signal VIN to an input terminal of the bootstrap unit, in such a manner that when an output of K0 is at high level, a voltage difference between a voltage V0 output by the bootstrap unit and a voltage of a signal VIN inputted thereof is a constant voltage VC, i.e., V0=VIN+VC, so as to improve the voltage outputted by V0; when the output of K0 is at low level, V0=0, (V0 outputted is at low level), i.e., the output voltage V0 of the input signal VIN which passes through the bootstrap unit is controlled by the clock circuit. An output terminal of the bootstrap unit is connected with a gate electrode of the FET M1, a source electrode of the FET M1 is connected with an external input terminal. When V0 is at high level, the FET M1 samples the input signal VIN of the external output terminal and outputs a VOUT via a drain electrode thereof. A first end of the capacitor C0 is connected with the drain electrode of the FET M1, a second end thereof is grounded, so as to maintain a voltage of a signal obtained by sampling of the FET M1, i.e., when the output terminal K0 of the clock circuit outputs a low level voltage to cause that V0 is at low level, the signal obtained by sampling of the FET M1 is not impacted and is maintained by the capacitor C0.
In the process mentioned above, a positive going input of the external input is set to be VIN1, and an inverted input thereof is VIN2. When the external input is the positive going input VIN1 and the output of K0 is converted from a high level to a low level, the voltage of V0 drops from a high level VIN+VC to 0, in such a manner that the FET M1 introduces the clock feedthrough which has following effect on the sampling signal:
                              Δ          ⁢                                          ⁢                      V            OUTP                          =                              -                                          C                                  P_GD                  ⁢                                      _                    ⁢                    M                    ⁢                    1                                                                                                C                                      P_GD                    ⁢                                          _                      ⁢                      M                      ⁢                      1                                                                      +                                  C                  0                                                              ⁢                      (                                          VIN                ⁢                                                                  ⁢                1                            +              VC                        )                                              (        1        )            
wherein CP—GD—M1 in the expression is a parasitic capacitance between gate electrode and drain electrode of the FET M1.
When the circuit adopts the fully-differential structure, the positive going input and the inverted input have same structures, so the invented input is VIN2 has an impact on the sampling signal as follows:
                              Δ          ⁢                                          ⁢                      V            OUTN                          =                              -                                          C                                  N_GD                  ⁢                                      _                    ⁢                    M                    ⁢                    1                                                                                                C                                      N_GD                    ⁢                                          _                      ⁢                      M                      ⁢                      1                                                                      +                                  C                  0                                                              ⁢                      (                                          VIN                ⁢                                                                  ⁢                2                            +              VC                        )                                              (        2        )            
wherein in the expression (2), since the clock pulses are converted from a low level to a high level, CN—GD—M1 is a parasitic capacitance between gate electrode and drain electrode of the FET M1 while under an inverted input, because the sampling circuit has a same structure during the positive going input and the inverted input, CN—GD—M1=CP—GD—M1=CGD—M1.
Combining expressions (1) and (2), a dynamic voltage of a differential sampling output signal is:
                              Δ          ⁢                                          ⁢                      V            DIFF                          =                                            Δ              ⁢                                                          ⁢                              V                OUTP                                      -                          Δ              ⁢                                                          ⁢                              V                OUTN                                              =                                    -                                                C                                      GD_M                    ⁢                    1                                                                                        C                                          GD_M                      ⁢                      1                                                        +                                      C                    0                                                                        ⁢                          (                                                VIN                  ⁢                                                                          ⁢                  1                                -                                  VIN                  ⁢                                                                          ⁢                  2                                            )                                                          (        3        )            
It can be seen from the expression (3) that: error of the differential sampling output signal brought by the clock feedthrough effect introduced by the parasitic capacitance between the gate electrode and the drain electrode of the FET M1 is proportional to the differential input signal, variation of the dynamic voltage is non linear and is not capable of being eliminated by the differential structure itself. In addition, the greater the parasitic capacitance of the EFT M1, the greater the amplitude of the input signal, and the more obvious of the nonlinearity introduced by the clock feedthrough effect, which has a serious effect on the accuracy of the differential sampling output signal.
Therefore, in order to overcome the shortcomings mentioned above, it is necessary to provide an improved sampling circuit for ADC.